A low-offset class-AB CMOS operational amplifier

This paper presents a novel systematic offset minimization circuit for designing a class-AB CMOS operational amplifier. The proposed structure has a replica-gain circuit, generating a DC replica bias to the differential input stage, and providing differential gain as well as level conversion to drive the class-AB output stage. Statistical measurements on 15 samples of the amplifier showed the mean and standard deviation of the input offset were of 0.88 mV and 0.49 mV respectively. These results were achieved using an active area of only 3700 /spl mu/m/sup 2/ for the critical differential input stage in a 0.8 /spl mu/m standard CMOS technology.