Reliability Analysis of Nano-CMOS Logic Gates Under Process Induced Variations

The continuous scaling of CMOS processes resulted in continuing reduction in device dimensions. As devices are scaled down, the process induced variations result in an unpredictable operation of CMOS circuits. The proposed work studies the impact of the reliability-performance tradeoffs at CMOS circuits due to device variability at gate level. Reliability indices or probability of failure of some commonly used logic gates are developed. The impact of scaling serially-connected transistors on the reliability of logic gates is presented.