High Performance Square Spiral Inductor for 65 nm CMOS V-band Low Noise Amplifier

A high performance parallel stacked, square spiral inductor with high resistivity silicon substrate is proposed in this work to achieve higher gain and lower noise figure (NF) in receiver sub-block, that is, low noise amplifier (LNA) designed at 53.5 GHz using standard UMC 65 nm CMOS technology. The LNA consists of four CS stages with current-sharing technique implemented in the last two stages to minimize power dissipation. Using the proposed inductor design, LNA achieves a gain of 29.1 dB, low NF of 4.1 dB at 53.5 GHz consuming a low power of 13.9 mW using 1.2 V DC supply. The proposed square spiral inductor is designed with 2.5 turns, inner diameter of 5.5 um, width of 1.5 um and with the observed area of 72×72 um achieves a Q-factor of 9.35 and inductance of 202.9 nH over V-band (40-75) GHz.