Top Gate Molding and Wire Sweep Improvement in Full Plastic QFP Packages

A method towards low cost chip assembly is by increase unit density per Leadframe with Top gate molding solution. In top gate molding, leadframe not require to dedicated space for mold runner in transfer process. That space will replace with more units by lower unit column-to-column pitch distance. Typical challenge of top gate molding is wire sweep especially on unit at Leadframe outer row. EMC injected into units on Leadframe outer row experiencing unbalance mold flow that challenging the molding process development. CAE simulation tool used to predict mold flow behavior and improvement runner design to minimize mold flow unbalance at end of transfer filling process. DOE experiment was perform to optimize transfer time range between 7.8s to 10.5s. Wire loop height optimization was perform as continuous improvement to improve wire sweep in QFP top gate molding from 10.47% to 7%.