Design and Analysis of a Novel 8X8 Bit Signed/Unsigned Synchronous MAC Architecture Using Clock Gating Scheme for Fixed-Point Arithmetic

Nowadays low power designs play a crucial role in any of the electronic devices. Many of the researchers are involved in the design of low power designs that play a crucial role in the digital signal systems. Out of these, Multiply-Accumulate unit is the basic block in digital signal processing systems. In this paper various MAC architectures along with its various sub blocks such as adder and multiplier are reviewed thoroughly. Novel MAC architectures for Unsigned MAC, Unsigned synchronized MAC and Signed MAC are proposed and implemented using CMOS 90nm technology using Cadence Virtuoso. A detailed comparison with respect to power and area is also done for the proposed architectures.