BDD Based Logic Synthesis and Optimization for Low Power Comparator Circuit

Low power can be achieved at various levels in design hierarchy: architecture to algorithm and logic level to device level. However substantial amount of power can be saved if it is targeted early in the design cycle. Logic optimization and synthesis play a significant role in this content. Experimentally it is seen that about 20% to 30% of total power can be saved at the logic level. In this paper BDD based optimization of a 4-bit magnitude comparator circuit considering the output has been presented and found to achieve our objective of power minimization. With BDD and pre-computation strategy a significant improvement can be achieved in terms of power. In pre-computation module the total power consumption comes out to be 24.40 μW and in BDD it is 13.89 μW, whereas comparator without any techniques the consumed power comes as 35.33μW. So we can conclude that applying a BDD logic synthesis and optimization we can save a substantial amount of power.