Modeling Power Vertical High-k MOS Device With Interface Charges via Superposition Methodology-Breakdown Voltage and Specific ON-Resistance

An analytical model for the power vertical MOS device with a high-k insulating dielectric (HKMOS) is derived via the superposition methodology on the condition of punchthrough. Considering three portions-the superjunction part, the p-i-n diode, and the interface charges at the heterointerface based on the conservation of electric displacement, the HKMOS device could be modeled well as verified by the 2-D simulation results.