An efficient way of implementing high speed 4-Bit advanced multipliers in FPGA

ALU in Digital processor is the important block as all the computational operations carried out by this. A multiplier is an electronic circuit used in any computing device for multiplication of two binary numbers. Multiplication of 4-bit numbers is a lengthy procedure if we go the conventional way. In this paper, two 4 bit multipliers purposed namely Unsigned Array Multiplier and Wallace Tree Multiplier. The Wallace tree method is highly pipelined and saves a lot of time. Individual components of both the devices are optimized and have been used to construct the multipliers. The designed circuit is implemented in FPGA (BASYS-3 ARTIX-7). The delay obtained in Wallace multiplier is 6.86ns,49.35
^%
reduction in delay compared to previous literature. Also, the power consumption is also very low(3.81watt) for Wallace tree multiplier.