Reliability Assessment of 10nm FinFET Process Technology

A systematic study of accurate reliability projection in lOnm FinFETs are discussed in this paper. As the semiconductor process technology continuously scales down to achieve optimum performance, reliability margin from the minimal spacing is also reduced. In many cases, conventional reliability modeling of BTI, HCI, and TDDB can be done but more effort can be put to improve the reliability modeling and characterization work to enable more critical space margin and verify through cleverly stressing it, thereby demonstrate the excellent product level quality and ensure reliability robustness.