DDR as KGD in 3D-IC M1 Short Failure Analysis

3D-IC is becoming more popular in recently years due to the advantages of lower cost and area saving [1]. A simple 3D chip is represented by stacking 2 dies which comprise of with a SOC (System on chip) die and a KGD (Known good die) memory die (DDR) in a single package chip. Although the architecture appears to be straightforward, failure analysis is significantly more challenging than a single die packaged chip [2]. This paper provides a systematic methodology for the failure debug on such a dual-die co-packaged chip. Based on board level electrical analysis and SAT/ 3D-Xay detection, a SOC die problem and interconnection problem can be excluded. The suspected DDR die can be taken out from the 3D-IC to be repackaged to a DDR chip. By testing this chip, memory register failures can be diagnosed. In the case study presented, Cu residues has been found between long routing M1line with min space at peripheral area after delayering PFA. A single wafer DHF clean step after M1 etch is introduced as a corrective fix to eliminate this residue. After this process optimization, Cu residues are proven to be removed and the 3D-IC chip passes the following reliability qualification.