A 110–125 GHz 27.5 dB Gain Low-power I/Q Receiver Front-end in 65 nm CMOS Technology

This paper presents a 120GHz low-power I/Q direct conversion receiver for chip to chip communication in a 65 nm complementary metal-oxide-semiconductor (CMOS) process. The proposed receiver integrates a 120 GHz low noise amplifier (LNA) with an active balun, a down-conversion mixer with a baseband amplifier, and a quadrature injection locked oscillator (QILO), all integrated on a single chip. The receiver exhibits a gain of 27.5 dB, a 3 dB bandwidth of 14 GHz, and an output P1 dB of -4.5 dBm. The gain mismatch and phase mismatch between the I channel and Q channel in the signal bandwidth are within 2.1 dB and 3.7 degrees, respectively. The simulated noise figure of the receiver is 17.7 dB at 120 GHz. The receiver consumes only 174 mW and has a chip size of 3.06 mm
²
.