Micro Bump System for 2nd Generation Silicon Interposer with GPU and High Bandwidth Memory (HBM) Concurrent Integration

Data intensive applications such as high performance computing (HPC) and artificial intelligence (AI) have recently become major subjects in industry. The heterogeneous integration of a chip and high bandwidth memories (HBMs) using through silicon via (TSV) based interposer has gained attractions to meet their performance requirements. An introduction of micro bump systems of these heterogeneous components (ex, a reticle limited GPU chip and HBMs) can created challenges in chip on wafer (COW) stacking. The impacts of heterogeneous micro bump systems and a giant GPU chip on COW stacking process are investigated in two micro pad systems. Micro bump system with adding a material layer or layers between Cu pillar and SnAg solder is found to be effective in modifying micro bump melting characteristics. It demonstrated the chip warpage dependent micro bump integrity. Micro bump joints formed by both micro pad systems passed reliability requirement without electrical, mechanical, microstructural failures.