A 0.75–3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector

This paper proposes a 750-Mb/s to 3.0-Gb/s dual-mode (full and half rate) referenceless clock and data recovery (CDR) circuit in a 65-nm CMOS process. The dual-mode deadzone-compensated frequency detector (DC-FD) and the digital calibration of both bank and control voltage of voltage-controlled oscillators (VCOs) allow precise frequency acquisition even with high input jitter. The dual-mode scheme extends supported data rates, and the temperature compensation technique allows uninterrupted video transmission with a bit error rate (BER) below 10
⁻¹²
over a wide temperature range from −20 °C to 120 °C.