New Multiplicative Inverse Architectures Using Gaussian Normal Basis

The multiplicative inverse over binary fields is one of main arithmetic operations used in cryptography. This paper presents two new inversion architectures. First, an improved architecture for classic inversion scheme using single multiplier is presented. The new improved inverter achieves lower latency through loading input registers during last multiplication cycle, at the expense of higher propagation delay. After this, a novel inversion architecture which uses half the latency to process the classic-based addition chains (or improved ones) is presented. The latter architecture, named Classical-Interleaved, is constructed based on a novel fully-serial-in square-multiply processor (FSISM). The FSISM, squares one operand, and multiply it to the second one, concurrently while the two inputs are absorbed serially digit-by-digit. The new classical inverter and the new classical-interleaved inverter reduce the latency compared to other schemes. In addition, the proposed classical and interleaved inverters outperform the original Itoh-Tsujii algorithm (ITA) and Ternary Itoh-Tsujii / optimal 3-chain algorithms in terms of its higher throughput and improved hardware efficiency for a number of digit sizes. The efficiency of the proposed field inverters are demonstrated by comparisons based on application specific integrated circuits (ASIC) implementations results using the standard 65 nm CMOS technology libraries.