An 18-GHz-bandwidth master-slave sample-and-hold amplifier for high-speed communication in 0.13um SiGe BiCMOS

Design and analysis of a fully-differential master-slave sample-and-hold amplifier (SHA) is presented in this paper using 0.13um SiGe BiCMOS process. To achieve broad bandwidth, Cherry-Hooper topology is employed in the input buffer of SHA. With feedthrough-attenuation capacitors and clock-controlled auxiliary transistors in track-hold switch, signal feed-through and clock feedthrough are reduced. To shorten trackhold transition time, sinusoidal clock signal is converted to square wave in clock buffer. Input bandwidth of 18GHz, spurious free dynamic rang above 33dB are measured for 2 GSample/s and -5dBm single-ended input signal. The proposed SHA is suit for high-speed high-broadband analog-to-digital converter used in high-speed wireless communication.