Performance optimized digital QPSK modulator

Quadrature Phase Shift Keying (QPSK) modulation is a popular digital modulation technique. Though it consumes less power and is quite compact as compared to other digital modulation technique, the objective of this paper is to propose a method for QPSK modulation which further reduces power consumption, reduces memory requirement and improves the speed of operation by increasing the maximum operating frequency. The proposed modulation method brings changes in Direct Digital Frequency Synthesizer (DDFS) block in the conventional QPSK modulation technique, which results in the improvement of various performance parameters. Here, the input is the bit sequence generated by a pseudorandom number (PN) generator and the output is the QPSK modulated signal.