Equivalent inverter-based characterization tool for nano-scale CMOS digital cells: Non-linear-delay-models evaluation

Fast and sufficiently accurate modeling of timing/power characteristics of CMOS logic cells facilitates significantly the design phase of integrated circuits. Recently, we presented an equivalent inverter-based modeling tool where an analytical inverter model with appropriate transistor widths provided accelerated (relative to conventional SPICE simulators) timing/power table-based characterizations for the combinational cells consisted in a nano-scale CMOS cell library. Here, we validate the NLDM models exported by our characterization tool in a benchmark circuit which consists of different CMOS gates connected in series. The reported errors further verify this modeling approach.