Investigation of carrier-induced defect behavior in p-type multicrystalline silicon

The underlying mechanism behind carrier-induced degradation in multi-crystalline silicon (mc-Si) solar cells remains unknown, however clues can be gained through studies of the behavior of the defect/s in response to different processing steps. Recently, surprisingly significant changes to the kinetics of the defect/s after low-temperature dark annealing have been observed for mc-Si PERC cells. In this study we apply the same processes to symmetrical lifetime test structures to validate that these changes to the kinetics are indeed caused by changes in the bulk of the wafers.