Self-Timed Shaper Circuit for Wide Memories in Advanced CMOS Technologies

In advanced processes, metal resistance is a limiting factor for performance. At high temperature, further increase in metal resistance causes pulse width evaporation in critical signals like wordlines (WL). In 16nm SRAM testchip, write failure due to high resistance on wordline was observed. This paper proposes a self-timed wordline shaper circuit which supplements wordline driver by charging the wordline from the opposite edge of SRAM array. Proposed circuit improves writability from 4.5 to 6 sigma bitcell variation and increases bitline differential by 30%. The proposed circuit is implemented with an area overhead of 0.4% for 640 columns per wordline.