Improved design of CMOS 1-bit comparator with stacking technique

This paper presents the design and analysis of a CMOS based efficient one bit comparator circuit. Comparator has been designed and simulated in 180nm TSMC technology. The proposed circuit uses a XNOR gate, two AND gates and two NOT gates. Stacking technique has been used to improve the conventional design. Power supply has been varied from 1.0V to 2.8V for the proposed and basic design. Result reflects that proposed approach shows less power consumption and improved power delay product (PDP).