Lopez Dahab based elliptic crypto processor (ECP) over GF(2163) for low-area applications on FPGA

In this paper, a novel low-area elliptic crypto processor (ECP) implementation over GF(2
¹⁶³
) for point multiplication (PM) is presented on field programmable gate array (FPGA) using polynomial basis representation. The novel architecture is based on Lopez Dahab PM algorithm. A bit-parallel hybrid karatsuba multiplier is used to reduce clock cycles (latency) and Itoh Tsujii inversion algorithm is used to reduce hardware resources. The proposed ECP architecture has been implemented on different Xilinx FPGA's i-e., Virtex 4, Virtex 5, Virtex 6 and Virtex 7 devices. The performance of proposed ECP in terms of area-to-time product is analyzed by using slices×k.P(s)/10
⁶
. Our proposed ECP achieves the lower area (slices) with comparable speed and area-to-time product on Virtex 4 (6884 slices, 53.5 μs, 0.368), on Virtex 5 (3636 slices, 32.3 μs, 0.117), on Virtex 6 (3144 slices, 26.9 μs, 0.084) and on newer Virtex 7 (3657 slices, 25.3 μs, 0.092). Finally, the proposed ECP outperforms on Virtex 6 in terms of both area (slices) and area-to-time product (0.084) when compared with most relevant state-of-the-art.