Reliability analysis on low temperature gate stack process steps for 3D sequential integration

In this study we investigate the effect of some of the steps during a low temperature gate stack process flow, necessary for 3D sequential integration. These are: the nitridation of the high-k layer, the post nitridation annealing temperature and finally, the back end forming gas. Using Time Dependent Defect Spectroscopy, we could evaluate the impact of pre-existing traps on the quality of the gate stack (t
₀
reliability) which shows no major differences between the splits, since they all have a low temperature dopant activation process. However, by applying Negative Bias Temperature Instability measurements, we observe that with the split of N
₂
/H
₂
nitridation, we have the best compromise of a small Equivalent Oxide Thickness and a low degradation. At the same time we see no difference at the stress impact between the two Post Nitridation Anneal temperatures. In that way we are able to move to lower temperatures. Finally, using the Deuterium as a back end forming gas we can have a set of guidelines, for some of the major process steps, to achieve high performance and low degradation, necessary for future scaling.