An optimized pipelined architecture of SHA-256 hash function

Real time applications of digital communication systems are rapidly increasing. Due to this there is a huge demand for high level of security. In cryptographic algorithms, SHA-256 has become an integral part in many applications. A hardware implementation of the SHA-256 hash algorithm is physically separate from the main processor and hence, it has more security and higher performance than the software implementation. An execution of a hash algorithm on FPGAs is convenient, as it is flexible and easily upgradable. However, implementation of this algorithm on hardware has been challenging, due to the demand of high processing speed. In this paper, an optimized pipelined architecture of SHA-256 hash function has been implemented in hardware HDL Verilog language and synthesized in Xilinx Virtex-4 FPGA. The compressor and expander block of hash function are modified. Carry skip adder is also used to improve the performance of the architecture. The obtained result shows a significant improvement in the performance of the proposed SHA-256 algorithm and it is compared with existing various architectures. Its maximum clock frequency is 170.75 MHz, throughput of 1344.98 Mbps and an improved efficiency of 2.2 Mbps/ slice.