FPGA implementation of viterbi decoder for software defined radio applications

Software defined radio adapts various modulation schemes, encoding techniques by changing its configuration. It has earned great attention in the recent years for its flexibility to adapt various techniques without the need of replacement of the existing hardware. SDR reduces the cost complexity and provides the flexible communication system. This paper presents the viterbi decoder architecture with improved trace back unit for a code rate of 1/2 and a constraint length of k = 3. This decoder finds advantages in software defined radio applications due to its area efficiency and speed. The proposed decoder is simulated in Xilinx 14.1 and implemented in a field programmable gate array (FPGA).