Redundant Arithmetic Based High Speed Carry Free Hybrid Adders with Built-In Scan Chain on FPGAs

Scan based error detection architectures for hybrid, carry-free radix-2 and radix-4 addition operations using redundant arithmetic are presented in this paper. Such addition operations have been chosen as representative examples as they are free from carry propagation delay and are ideal from the viewpoint of technology mapping of the logic elements onto the FPGA slices. The architectures have been conceived following the design paradigm of target FPGA specific primitive instantiation coupled with location constraints, without any degradation in the speed of circuit operation as compared to the original circuit implementation without the scan operation. Our architectures also comfortably outperform the existing state-of-the-art error detection architectures in terms of speed and consumes less area.