Comparative analysis of 2T, 3T and 4T DRAM CMOS cells

In this paper various popular topologies of DRAM cells are designed and analyzed on deep submicron technology. Now a days in all digital data processors and controllers memory blocks have become decisive part for overall performance of system. Selecting a DRAM cell topology from all available types significantly increases design time and efforts. Some popular DRAM topologies are 2T, 3T and 4T cells. In above context, performance analysis and comparison of 2T, 3T and 4T DRAM cells have been carried out in this work. Concerned cells are compared on the basis of their read access time, write access time, retention time and power dissipation. All design and simulation work has been performed on Tanner EDA tool.