A $D$ -Band Two-Element Phased-Array Receiver Front End With Quadrature-Hybrid-Based Vector Modulator

This letter presents a D-band two-element phased-array receiver (Rx) front end implemented in a 0.13-μm SiGe BiCMOS process. The Rx employs a low-loss quadrature-hybrid-based power-domain phase interpolator for a power-efficient multibit phase synthesis. The measured average gain is 13 dB with a peak gain of 15.6 dB at 115 GHz and rms gain variation over 4-bit phase states is <;1.6 dB. The measured rms phase error is <;5° at 115 GHz. The overall dc power consumption (P
_diss
) of the single Rx channel is 53 mW from 2.2-V supply. The core chip size of the two-channel Rx is 1.7 × 1.24 mm
²
.