Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs

The increased penetration of FPGAs into automotive applications demand stringent defect coverage levels for FPGA IPs. The increased use of FinFETs and the possible defects thereby, motivates the usage of cell-aware methods to improve the defect coverage levels during testing. Simulation results on 16 nm 30 million gate Zynq® MPSoC system demonstrate the effectiveness of top-off based cell-aware methods in terms of test coverage, pattern volume and ATPG runtime simultaneously. Silicon results on 20nm and 16 nm Xilinx FinFET-based FPGAs show the effectiveness of cell-aware methods in catching test escapes.