Identification of Efficient Clustering Techniques for Test Power Activity on the Layout

With the increase in transistor density in state-of-the-art circuits the power behavior of integrated circuits changes drastically, which may result in device failures. This may become worse while testing, because of the high transient activity in smaller area. This may lead to high power consumption and failures in certain areas as compared to other parts of the die. For this reason, high power density areas on the integrated circuits need to be identified on the layout to avoid effects such as IR-drop, EM and noise as early as possible. Previously, this was usually considered by manually dividing the layout in equal blocks. However, this method may not provide the desired accuracy due to e.g. boundary effects and manual errors. In this paper, we propose the use of pattern recognition/machine learning techniques to dynamically partition the layout in clusters to identify high power density areas under test application. We show how machine learning techniques can be used to model the clustering problem and analyze the feasibility as well as the performance of several algorithms on benchmark circuits. These techniques avoid the errors on static boundaries and account for pattern dependent behavior. Furthermore, the proposed clustering is validated by comparing the results to a contour of an industrial tool.