Effective critical gate identification for mitigating circuit aging using gate replacement

NBTI effect has become a major problem for device reliability in Nano CMOS technology. The aging issue of logic gate caused by NBTI can be alleviated by gate replacement techniques. This paper proposes an efficient metric to identifying the critical gates and an improved gate replacement algorithm. Firstly, an aging analysis framework considering the internal nodes information of the circuit is developed. The metric introduces a need consider view of the critical gate's output changes may affect subsequent logical gate to identify critical gates. Finally, the improved gate replacement algorithm is applied to replace the critical gates in circuit. Experimental results based on 45nm transistor process model and ISCAS85 benchmark circuit show that, compared with the existing gate replacement techniques, the proposed methods can identify the critical gates more accurately with the average delay improvement rate of 25.11% with less overhead.