Laboratory jitter removal circuit for single-bit all-digital frequency synthesis

All-digital frequency synthesizers based on sigma-delta modulation with single-bit output can have exceptionally high dynamic range and spurs-free dynamic range, in simulation. The performance of their FPGA implementations however is significantly limited by the jitter introduced by the FPGA and its clock reference, which is translated to phase noise. This paper introduces a laboratory circuit architecture for suppressing the FPGA and reference jitter in order to achieve spectrally cleaner single-bit output sequences and demonstrate the achievable performance of the all-digital frequency synthesizers. The proposed architecture is based on a 1-Bit DAC re-clocking the singlebit digital output of the FPGA using one of the two low-jitter clocks generated by a low phase noise reference oscillator. The second clock is used to clock the FPGA after passing through a programmable delay line and a small-value frequency divider. The implementation of the circuit's architecture is presented discussing the design challenges. Phase noise measurements demonstrate the performance of the circuit. Spectral measurements illustrate the effectiveness of jitter removal in the case of a sigma-delta modulator single-bit output.