Electrical modeling of 3D stacked TSV

3-D integration technologies have been of increasing interest for compact and high-performance system integration and packaging. Through-silicon-via (TSV) is one of the key technologies to enable vertical connections for stacked ICs and silicon packages. In the recent years, the annular via and taped via geometries have been the focus for industry research institutes and has been demonstrated to have lower electrical resistance and better thermal stability. Different TSV physical structures such as cylindrical, tapered, annular are analyzed using the FEM based EM simulator HFSS in this study. In addition to the TSV shape impact on the performance of TSV signal transmission, the effect of substrate conductivity on the signal transmission is investigated in this study.