A method to speed up VLSI hierarchical physical design in floorplanning

With the rapid increase in size and complexity of VLSI, it is hard to meet speed and quality requirement of IC physical design. In this paper, we present an efficient model for quick floorplanning in VLSI top-down hierarchical physical design flow using the Active-Logic Reduction Technology. The simplified model replaces some original modules in netlist file with filling units which have no logical connections. This method can effectively reduce internal logical units and quickly predict if chip design achieves timing closure after top and blocks implementation with this floorplan so as to quickly judge the floorplan's quality. Most importantly, it can maintain design quality while speeding up design flow. The results of six experiments show that the method can drastically reduce runtime by 6.2 times and memory by 2.8 times on average in VLSI hierarchical physical designs.