Sensitivity of reliability of logic gates

Ever-shrinking dimensions of transistors in CMOS have caused the failure rates/probabilities to increase dramatically. Monte Carlo simulations are one way of estimation the failure probabilities, however, such simulations tend to be very time-consuming. A much speedier alternative is to use models for the estimation. This paper presents a method for creating the mathematical models for the probabilities of failures of CMOS logic gates/blocks. The models of five common gates are included, i.e., NAND3, NAND4, NOR3, NOR4 and OAI22. The models can also be used to study the sensitivity of the gates' failures to their individual transistors' failures. The presented technique is applicable to larger logic cells such as 28-transistor full-adders, etc. The given models are anticipated to be useful for Pareto-optimization of logic blocks, for instance, power-and-reliability, performance-and-reliability etc.