Simulations and comparisons of basic analog and digital circuit blocks employing Tunnel FETs and conventional FinFETs

In the past decade the Tunnel Field Effect Transistor (TFET) relying on band-to-band tunneling (BTBT) has emerged as one of the most promising small slope FETs able to achieve a subthreshold swing (SS) below the room temperature 60 mV/dec limit of conventional MOSFET. Many simulation studies attributed to TFETs the potential to outperform conventional MOSFETs in the ultra-low voltage domain (V<;sub>DD<;/sub> <; 0.4 V) in both analog and digital applications. However, only basic digital and analog circuits have been fabricated up to date, such as current mirrors and inverter gates. As for semiconductor materials, III-V hetero-structure TFETs may be able to achieve a sub-thermal SS in a wide current range and, at the same time, very competitive on currents, as demonstrated by a recently fabricated vertical InAs/GaAsSb/GaSb nanowire n-type TFETs. The aim of this work is to benchmark a complementary III-V TFET technology platform against the mainstream FinFET reference, by considering basic building blocks of digital and analog applications. To this purpose, we selected a complementary III-V TFET technology platform designed and optimized using full quantum simulations in [11], where nand p-type TFET pairs are realized in the same InAs/AlGaSb material system. The use of such devices allowed us to remove the excessively optimistic assumption of perfectly symmetric nand p-type TFETs, very frequently embraced in previous simulation studies (e.g. in [2, 7]). We present circuit-level simulations performed on current mirrors and inverter-based logic blocks, which are identified as basic topologies representative of the analog and digital design realms, respectively. Similar benchmarking results for the same technology platforms have been obtained by focusing the comparison on more complicated circuit blocks [3], [5] and [6].