Improvement of board level reliability for fine pitch PoP

With the rapid growth in the mobile industry, Package-on-Package (PoP) technology has been widely adopted for the 3D integration of logic and memory devices within mobile handsets and other portable multimedia products. The PoP solution offers significant advantages, including increased density through stacking logic and memory devices in the same formfactor and a high degree of flexibility for variable memory devices. Recently, a thinner PoP structure is strongly required with finer memory interface (MIF) pitch for mobile applications. Currently, a 0.35 mm MIF pitch for Through Mold Via (TMV®) is in production and fine MIF less than 0.35 mm pitch is under development for higher memory I/O density. However, as package thickness gets thinner and the MIF pitch gets finer, warpage control and interconnection reliability performance become more critical. In this paper, a comprehensive study has been performed including package design, structure, materials with process conditions. As a result, advanced PoP structure is proposed that enables minimum warpage and better board level reliability (BLR) performance.