ASIC implementation of shared LUT based distributed arithmetic in FIR Filter

This paper presents a brief on the implementation of reconfigurable shared LUT (look-up-table) based Distributed Arithmetic (DA) for the higher order finite-impulse response (FIR) filters whose filter coefficients can be changed during run time. In this architecture all the multipliers and adders are replaced by the register banks, multiplexers and the shifters. The throughput rate of the design is increased by having shared LUTs instead of ROM in the DA FIR filter architecture. By implementing this concept in ASIC, the area, area delay product (ADP), minimum cycle period (MCP) and energy per sample are reduced when compare with the conventional DA architecture. The architecture supports 95 MHz sampling frequency.