The importance of the internal bulk-source potential on the low temperature kink in NMOSTs

The kink occurring at low temperatures in the I/sub DS/-V/sub DS/ curves of NMOS transistors is explained by the direct correlation between the current injected into the source, the internal bulk potential, and the resulting change in threshold voltage. A semi-two-dimensional analytical model is derived for calculating the influence of the multiplication current from room temperature down to liquid-helium temperature. Only steady-state equations are derived and no time effects are included. The proposed model gives the possibility of quite accurately calculating the influence of the device geometry. Extension to the case of silicon-on-insulator (SOI) transistors is also briefly discussed.<
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