Degradation of 4H-SiC MOSFETs under different short circuit test conditions: A simulation study

The influence of different short circuit (SC) test conditions, including bias voltages and case temperature, on the degradation of Silicon Carbide (SiC) MOSFETs performance is investigated. Sentaurus TCAD is utilized with the trap degradation model included in the simulations to assess the density of hot holes trapped in the gate oxide during this procedure. Simulation results demonstrate that higher temperature and drain bias voltage will result in faster degradation while a degradation extremum exists with the increase of gate voltage.