Measuring Metastability with Free-Running Clocks

With the increasing number of clock domain crossings in modern VLSI circuits, the area, power and performance overheads introduced by synchronization have a rising impact on the overall system parameters. To minimize these overheads while still reaching the targeted system reliability, it is very important to precisely know the parameters of the circuit elements used for synchronization regarding metastability. While it is well understood, what parameters are relevant and how they can be derived from circuit models, obtained from simulation or even measured, the state of the art measurement approaches require precisely timed clock inputs. These are typically provided with expensive test equipment, on-chip clock management blocks or calibrated delay lines. This paper proposes an approach for measuring metastability parameters using uncorrelated free-running clocks only at the expense of a more challenging post-processing. The principle is closely related to sampling oscilloscopes with the same fundamental property: the measurement resolution is theoretically unbounded but proportional to the measurement time. Apart from the description of the circuit, this paper includes an analysis of the effect of clock uncertainty (jitter) on the measurement result and an experimental evaluation.