A Workload Sensitive Dynamic Scaling Matrix Multiplier Structure

Matrix multiplication is one of the most widely used computational kernels in scientific computing and machine learning. Using dedicated circuit for matrix multiplication can reduce the computational time and energy consumption. Traditional matrix multipliers always adopt linear array architecture, which works inefficiently when the size of matrix sub-block is much smaller than the array length. Using short array structure can improve the computational efficiency at the cost of occupying more memory bandwidth. In this paper, we present a workload sensitive dynamic scaling matrix multiplier structure, which can dynamically adjust the array length according to the matrix size. We build a prototype system on a Xilinx Zynq XC7Z045 FPGA. The result shows that compared with a fixed array architecture our design achieves much better performance and needs less memory bandwidth.