Defects and reliability of high K gate stacks on Si, Ge and III–Vs

To date, gate stacks for high mobility semiconductors like Ge and InGaAs have been generally designed to minimise their interfacial trap density, and thus include an Al oxide layer diffusion barrier as a component. However, this is now known to lead to reduced reliability. The source of the problem is discussed and possible solutions based on an AlN or AlON layer component are suggested instead. First, we discuss traps in HfO2-based gate stacks for Si and their reliability.