A low power dynamic logic with nMOS based resistive keeper circuit

Designing VLSI circuit using dynamic logic is one of the most area efficient techniques. However, the performance of the dynamic logic is not so promising due to longer time delay and higher leakage power. This research proposes a new model of dynamic logic by incorporating nMOS based resistive gate circuit. The proposed circuit reduces the contention time delay and the leakage power. Extensive simulation results using LTSpice tools demonstrate the validity and superiority of the proposed circuit.