Improved switched capacitor cell for a 3 GHz 20 GS/s waveform digitizing ASIC

Detectors in high energy physics (HEP) that are subject to high hit rates require fast and sophisticated instrumentation. The proposed Timing Vertex Detector (TVD) requires femtosecond resolution timing to determine the space-time coordinates of the traversing particles. One of its key components is the RFpix waveform digitizing ASIC, which is being designed to operate with an analog bandwidth of 3 GHz and sampling speed of up to 20 GS/s. The RFpix sampling architecture is based on switched capacitor arrays (SCA), which provide high channel density and low power. In this paper, analysis results of a sampling cell pertaining to a similar ASIC called PSEC4 are presented and compared to the simulation results of an improved sampling cell, designed to meet the RFpix requirements.