Scalable models to represent the via-pad capacitance and via-traces inductance in multilayer PCB high-speed interconnects

Closed-form expressions for the capacitance and inductance related to vias (vertical transitions) in interconnects implemented in PCB technology are presented. The importance of this contribution relies on the fact that these parasitic effects critically impact the performance of data channels by introducing undesired signal reflections. The development of the proposal is based on the systematic analysis of measurements and 3D electromagnetic simulations of actual high-speed links. Hence, a set of physically-based equivalent circuit models valid for different via pad sizes (scalable models) is obtained. This allows for the performance assessment and optimization of electrical transitions in channels in a fast and accurate way.