Electromigration-Aware Local-Via Allocation in Power/Ground TSVs of 3-D ICs

With increasing temperature and current density, electromigration (EM) becomes a major interconnect reliability concern for 3-D integrated-circuits (3-D ICs). In 3-D power delivery networks, local vias are used inside power/ground (P/G) through-silicon-vias (TSVs) for vertical power delivery, which are susceptible to EM effects. In order to improve the EM reliability of P/G TSVs, it is desirable to insert multiple local vias in each P/G TSV whereby the current density of each local via can be reduced. However, excessive local vias may consume too much routing area, which leads to exacerbated routing congestion and increased delay overhead. In this paper, we propose a design technique to handle this tradeoff between EM reliability of P/G TSVs and timing performance of 3-D ICs. By utilizing an integer-linear-programming formulation, the optimal local-via number in each P/G TSV can be determined to minimize the local via-induced routing congestion while satisfying the given requirement of EM reliability.