Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures

The confinement of carriers in a MOS-gated Ge/sub x/Si/sub 1-x/ heterostructure is numerically modeled. The structure uses a MOS gate to modulate the hole density at a buried Si/sub x//Ge/sub x/Si//sub 1-x/ interface. The number of holes in the well is modeled as a function of structure and gate bias. The hole confinement is then confirmed by capacitance-voltage and Hall measurements. Numerical modeling is used to predict the maximum number of carriers achievable at the interface as a function of the structural design, and clear experimental evidence for such carrier confinement is given.<
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