Development of a half-inch wafer for minimal fab process

Specifications and fabrication process suitable for a small wafer with the diameter of half-inch, which is used for a minimal fab, is presented. We beveled wafer edge by rapping and polishing in order to clean the edge and to suppress the strong surface tension at the edge. To show the crystallographic orientation of the wafer, we introduced laser marking process. By the processes, we have formed silicon wafer that is suitable for fabricating electronic devices. Formed MOS capacitor on the wafer revealed that the density of interface states (D
_it
) was 7.8×10
¹⁰
states/cm
²
as the average of 37 wafers.