Memory Based Floating Point FFT Processor Using Vedic Multiplication for Pulse Doppler RADAR

A radix -2 based 32 bit memory based floating point FFT processor using Vedic multiplication for pulse Doppler RADAR is presented in this paper. In proposed architecture twiddle factor is stored in memory. This architecture uses Urdhvtiryakabhyam sutra for multiplication process. Due to this computational complexity of FPGA gets reduce because it provides an external multiplication module to the FPGA tool and area required also gets reduces. This is a performance enhancement strategy because it reduces propagation delay of circuit and also reduces transmitted power and area required. Propagation delay of the proposed architecture at 40MHz frequency is 200ns. Hence latency of circuit gets increases. Hardware Simulation is done on Xilinx ISE simulator 14.2 and test bench results are received on Xilinx isim simulator.