Design of area-efficient multiple-output switched-capacitor DC-DC converters

This paper presents a general methodology to generate multiple outputs for different switched-capacitor DC-DC converters. By enabling the sharing of power switches and capacitors among outputs and the power-switch current-stress minimization, the required number and size of power switches and capacitors are minimized to optimize the area efficiency of the power converter. Experimental results demonstrate that a Dickson-based dual-output converter implemented in a standard 0.35μm CMOS process generates two independent outputs of 2V and 3V with a peak power efficiency of 89.5%. Both Ladder-based and Series-Parallel-based dual-output converters are also developed by using the proposed design strategy with proper operations.